National University of Singapore · Electrical & Computer Engineering
我研究氧化物晶体管：它们为什么会变得不稳定，以及怎样让它们足够可靠，可以被一层层堆叠在硅芯片之上。 I study oxide transistors — why they become unstable, and how to make them reliable enough to be stacked, tier upon tier, above silicon chips.
四个步骤，从器件结构讲到我的研究。向下滚动即可。Four steps, from device structure to my research. Scroll to advance.
ITO、IGZO 这类氧化物半导体可以在低温下沉积，因此能直接做在已完成的硅电路之上，而不损伤下面的器件。栅极电压决定沟道里能流过多少电流。Oxide semiconductors such as ITO and IGZO can be deposited at low temperature, so they can be built directly on top of finished silicon circuits without damaging them. The gate voltage sets how much current flows through the channel.
读图：转移曲线 ID–VG，阈值电压 VTH 是器件“开启”的位置。Reading the plot: the ID–VG transfer curve. The threshold voltage VTH is where the device turns on.
在正栅偏压和高温应力下，电子被栅介质及界面附近的陷阱俘获，使 VTH 正向漂移；与此同时，来自栅侧的氢扩散进入沟道，作为浅施主提供额外电子，使 VTH 负向漂移。两种机制同时存在、相互竞争，器件的开关点因此难以预测。Under positive gate bias and elevated temperature, electrons are captured by traps in the gate dielectric and near the interface, shifting VTH positive. At the same time, hydrogen from the gate side diffuses into the channel and acts as a shallow donor, shifting VTH negative. The two compete, so the switching point becomes hard to predict.
+ΔVTH：电子俘获 · −ΔVTH：氢施主+ΔVTH: electron trapping · −ΔVTH: hydrogen donors
我用原位生长的 NiO 插层在栅侧调控氢，让它不再进入沟道。在 5 MV/cm、415 K 下应力 1 ks 后，|ΔVTH| 低于 5 mV。An in-situ NiO interlayer regulates hydrogen on the gate side, keeping it out of the channel. After 1 ks of stress at 5 MV/cm and 415 K, |ΔVTH| stays below 5 mV.
IEEE EDL 2026 · DOI ↗器件稳定之后，还要能精确设定它的阈值。室温氟化提供了一种低成本、后道兼容的阈值调控方法，用它制作的反相器达到了 2687 的创纪录增益和较高的噪声容限。Stable devices also need a precisely set threshold. Room-temperature fluorination offers a low-cost, BEOL-compatible way to tune it; inverters built this way reach a record gain of 2687 with high noise margin.
IEEE EDL 2026 · DOI ↗从材料与界面，到器件的实际表现。From materials and interfaces to device behavior.
偏压和温度应力下，晶体管的阈值为什么会漂移？我研究氟钝化与栅侧界面工程如何影响这些退化过程。Why does transistor threshold voltage drift under bias and temperature stress? I study how fluorine passivation and gate-side interface engineering affect these degradation processes.
后道集成不能依赖高温处理。我研究用室温氟化调节器件阈值，并通过反相器验证它在逻辑电路中的应用。BEOL integration limits the thermal budget. I investigate room-temperature fluorination for threshold control, with inverter demonstrations connecting device engineering to logic circuits.
从液氮温度到高温，器件的可靠性如何随温度变化？这关系到器件能否在真实的工作环境中稳定运行。How does reliability evolve from cryogenic to elevated temperatures? The answer determines whether devices hold up across real operating conditions.
合作研究还涉及氧化物器件的短沟道效应与存储应用：Collaborative work also examines short-channel effects and oxide memory: 区分偏压应力效应与真实 DIBL ↗distinguishing bias-stress artifacts from intrinsic DIBL ↗
已接收，待发表。此处仅按会议公开摘要介绍研究主题。Accepted, forthcoming. Theme described from the public conference abstract only.
通过栅侧界面工程调控氢相关不稳定性。Gate-side interface engineering for hydrogen-related instability.
研究氟处理器件的可靠性及宽温区行为。Reliability and wide-temperature behavior of fluorine-treated devices.
通过室温氟化调控器件阈值，并验证高增益反相器。Room-temperature fluorination for threshold control and high-gain inverter demonstrations.
按研究主题介绍，链接指向正式论文。Summarized by research theme; links to the published paper.
按研究主题介绍，链接指向正式论文。Summarized by research theme; links to the published paper.
按研究主题介绍，链接指向正式论文。Summarized by research theme; links to the published paper.
* 表示共同贡献。* Equal contribution.
我的研究从洁净室里的器件制备开始，接着做电学与材料表征，最后回到数据和器件物理。My research starts with cleanroom fabrication, continues through electrical and materials characterization, and returns to data and device physics.
在 NUS，我研究缺陷、氢和栅侧界面怎样影响器件稳定性。我也是 E6 洁净室的设备高级用户，参与编写操作规范、培训新用户，并担任 IEEE Electron Device Letters 审稿人。At NUS, I study how defects, hydrogen and gate-side interfaces affect stability. I am also a designated tool superuser in the E6 cleanroom, contributing to operating procedures and new-user training, and a reviewer for IEEE Electron Device Letters.
欢迎联系我讨论研究合作、器件与工艺研发，或职业机会。Research collaboration, device and process R&D, or career opportunities.